Mercury Research: AMD closes 2021 with record x86 CPU market share at 25.6%
Intel x86 Processor and Platform Architecture eLearning Course
Intel x86 Processor and Platform Architecture eLearning Course
Instructor(s): Jay Trodden
Number of Modules: 52
Subscription Length: 90 days
Course Price
$995.00 Bundle Price (Course & Arbor)
$1,395.00
(more info on Arbor)
Intel x86 Processor and Platform Architecture eLearning Course What's Included? Course eLearning modules
(unlimited access for 90 days) PDF of Course Slides
(yours to keep, does not expire) x86 ISA eBook
(yours to keep, does not expire) Benefits of eLearning: Access to the Instructor - Ask questions to the MindShare Instructor that taught the course
- Ask questions to the MindShare Instructor that taught the course Cost Effective - Get the same information delivered in a live MindShare class at a fraction of the cost
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This in-depth course is a "must" for anyone dealing with designing, verifying, validating, debugging, or developing for x86-based platforms. The x86 instruction set architecture and platform architecture have evolved over a period of almost 40 years. This course describes the current architectures but also explains how we got to the current architecture based on the history and decisions made. It doesn't matter whether you're a hardware engineer or a software developer, this course has an enormous amount of relevant info for you. Course Outline: Module 1: Course Introduction
- Scope of course, outline, Arbor introduction
Module 2: Intel x86 Platform Background
- Walks through x86 CPU evolution
Module 3: Introduction To Platform Examples
- Describes general characteristics and differences between server platforms, desktop platforms and tablet platforms
Module 4: Haswell Core i7-v4 Desktop
- Discusses high-level CPU features as well as busses off processor package and PCH (PCIe, DMI, Video, USB, HD audio, ethernet, SATA, SPI Flash, SMBus, and more)
Module 5: Haswell E5-2600 v3 Server
- Discusses high-level CPU features and multi-socket systems as well as busses off processor packages and PCH (PCIe, DMI, BMC, USB, HD audio, ethernet, SATA, SPI Flash, SMBus, and more)
Module 6: Broadwell Core M SOC Tablet
- Discusses high-level CPU features and concept of Multi-Chip Package (MCP) as well as general features of tablet platforms
Module 7a: Broadwell Xeon E7-8800 v4 Server
- Discusses high-level CPU features and multi-socket systems as well as busses off processor packages and PCH (PCIe, DMI, BMC, USB, HD audio, ethernet, SATA, SPI Flash, SMBus, and more)
Module 7b: Cascade Lake-SP 2S Server
- Discusses high-level CPU features and multi-socket systems as well as busses off processor packages and PCH (PCIe, DMI, BMC, USB, HD audio, ethernet, SATA, SPI Flash, SMBus, and more)
Module 8: x86 Instruction Set Overview
- x86 instruction basics, instruction variants, integer operations, floating-point operations, MMX, SSE, AVX, program flow-related instructions, hardware-related instructions, x86 instruction format
Module 9: x86 Register Set Introduction
- Registers per thread (logical processor), general-purpose registers, flags register, x87 registers, MMX registers, XMM registers, YMM registers, ZMM registers, segment registers, control registers, debug registers, model-specific registers (MSRs)
Module 10: x86 CPU Operating Modes
- Real Mode, (legacy) Protected Mode, Virtual-8086 Mode, System Management Mode, Compatibility Mode, 64-bit Mode, Long Mode (IA-32e Mode) vs Legacy Mode
Module 11: Platform Addressing
- Memory space (system memory vs. memory-mapped IO: MMIO), IO space, PCI config space
Module 12a: CPU Memory Segmentation Part A
- Memory accesses, address generation (effective address, logical address, linear/virtual address, physical address), Real Mode segmentation
Module 12b: CPU Memory Segmentation Part A
- Code and Data segment descriptors, Global Descriptor Table (GDT), Local Descriptor Tables (LDTs), descriptor cache, flat memory model, Intel64 segmentation, long bit (CS.L)
Module 13a: Paging and TLBs
- Paging concepts and basic paging implementation in x86 architecture, on-demand paging example
Module 13b: Paging and TLBs
- x86 paging facts and page sizes: 4KB, 2MB, 4MB, 1GB, details of PTE, PDE, PDPE, PML4E, Page Size Extensions (PSE), Physical Address Extensions (PAE), Long Mode paging (Page Map Level 4 - PML4), intro to Processor Context ID (PCID), paging access rights determination, protection keys, execute disable (aka no execute)
Module 13c: Paging and TLBs
- Purpose of Translation Lookaside Buffers (TLBs), TLB behavior, global pages, contents of TLB entry, managing TLBs (INVLPG, INVPCID, INVVPID, MOV CR0, CR3, CR4), TLB shootdowns
Module 14: CPU Internal Architecture Overview
- Package resources per core vs shared, caches, instruction pipeline, local APIC, system agents (L3, power control unit, integrated memory controller, etc.), NUMA introduction
Module 15: CPU Microarchitecture
- Description of pipeline stages, instruction fetch, branch prediction, instruction decode, macro-op and micro-op fusion, uCode ROM, uOp cache, register files, load/store buffers, reorder buffer (ROB - retire order buffer), reservation stations, execution units
Module 16: Cache Basics
- Intro to caching, cache lines, evictions, intro to memory types and assigning of memory types (Memory Type and Range Registers - MTRRs; and Page Attribute Table - PAT)
Module 17: CPU Conduct In Cache Regions
- Behavior when operating in Uncacheable (UC) space, Write Combining (WC) space, Write Through (WT) space, Write Protect (WP) space and Write Back (WB) space
Module 18: Cache Hardware Architecture
- Common structure/layout of L1 Data cache (L1D), L1 Code cache (L1C), L2 cache, L3 (LLC) cache, Data Direct IO (DDIO) behavior
Module 19: Cache and Memory QoS
- Cache Monitoring Technology (CMT), Cache Allocation Technolgy (CAT), Code and Data Prioritization (CDP), Memory Bandwidth Monitoring (MBM)
Module 20: Other Cache Topics
- L4 cache option, non-temporal stores, software prefetch instructions, TLB sizes
Module 21: CPU and PCH Interface Overview
- Overview of key interfaces off processor package and PCH
Module 22: Main Memory DRAM
- Converting from system memory address to Rank (chip select) / Bank / Row / Column, error handling, DDR4 vs DDR3, example DDR transactions
Module 23a: QuickPath Interconnect (QPI)
- QPI intro, packets, flits, phits, coherent vs non-coherent traffic, source snooping protocol, home snooping protocol
Module 23b: QuickPath Interconnect (QPI)
- Home snooping protocol, DMA operations and QPI interaction
Module 24: PCI Express (PCIe)
- PCIe intro, link characteristics, types of devices (Root Complex, Root Complex Port, Switch, Native Endpoint, Legacy Endpoint, Bridge), device layers (Transation Layer, Data Link Layer, Physical Layer)
Module 25: PCI Configuration Space
- PCI configuration space, capability structures, PCI enumeration process
Module 26: Interrupts - Intro and Controller History
- Intro to interrupt handling, hardware interrupts vs software interrupts vs exceptions, interrupt vectors, locating handler via Interrupt Descriptor Table, 8259A interrupt controller basics, intro to APIC / IO APIC and xAPIC
Module 27: Interrupts - Local APIC Basics
- Local APIC registers, x2APIC, priority among hardware interrupts, masking interrupts based on priority threshold (TPR), behavior of local APIC
Module 28: Interrupts - Delivery Options
- APIC IDs (physical APID ID and logical APIC ID), physical destination mode, logical flat destination mode, logical cluster destination mode, redirectable interrupts, power aware interrupt remapping (PAIR)
Module 29: Interrupts - MSI, Interrupt Remapping and IPIs
- Message Signaled Interrupts (MSI), address and data encodings for x86 platforms, setting up MSI info at devices (PCI config space), MSI-X, purpose of interrupt remapping and overview of concept, Inter-Processor Interrupts (IPIs)
Module 30a: Overview of Virtualization Support
- What is virtualization, different approaches (application level vs machine level), software solutions (ring deprivileging, binary translation, paravirtualization), Intel VT-x, virtual machine control structure (VMCS), Intel VT example usage
Module 30b: Overview of Virtualization Support
- Memory and virtualization (shadow page tables vs extended page tables - EPTs), intro to VT-d features (IO virtualization)
Module 31: CPU Performance Monitoring
- Core performance monitoring, performance monitoring counters, fixed function vs general purpose monitoring, precise event based sampling (PEBS), uncore performance monitoring
Module 32: Machine Check Architecture (MCA)
- MCA error detection and reporting, MCA error classes (corrected and uncorrected), MCA-related interrupts, MCA registers, MCA banks
Module 33a: System Management Mode (SMM)
- Purpose of SMM, System Management Interrupt (SMI), sources of SMI
Module 33b: System Management Mode (SMM)
- SMRAM, Multi-core / multi-CPU behavior, protecting SMRAM, SMM operation considerations, latency, security, cache management, setting up PCH for SMI, SMM example
Module 34: Microcode Update
- Need for microcode updating, update procedure
Module 35: PCH: Internal Architecture
- Overview of internal blocks within a PCH
Module 36: PCH: USB Interface
- Overview of USB 2.0, USB 3.x and xHCI, USB topologies, hubs
Module 37: PCH: SATA Interface
- Overview of Serial ATA
Module 38: PCH: SMBus Interface
- Overview of System Management Bus
Module 39: PCH: SPI
- Overview of Serial Peripheral Interface
Module 40: Platform Power Management
- ACPI overview (global states, system states, etc.), C-state meaning and transitions, P-state meaning and transitions, Enhanced Intel SpeedStep (EIST), Turbo Boost
Module 41: Platform Thermal Management
- Digital Thermal Sensor, thermal management registers, thermal control circuit (TCC), thermal interrupt, adaptive thermal monitor (ATM), clock modulation, Vcc adjustments, thermal trip, PECI
Module 42a: Intel Optane Memory
- Problems addressed by Intel Optane memory, multi-tiered computer storage, mass storage performance gap, DRAM vs mass storage cost gap, non-persistent memory, Intel Optane features, 3D xPoint, five Intel Optane use cases
Module 42b: Intel Optane Memory
- Use case 1, client / workstation SSD, use case 2: SATA HDD acceleration, use case 3, hybrid SSD
Module 42c: Intel Optane Memory
- Use case 4, Intel Optane DC SSD as main memory, use case 5, Intel Optane DCPMM (persistent memory module) Course Modules Module Length Module 1: Course Introduction 17 minutes Module 2: Intel x86 Platform Background 16 minutes Module 3: Platform Information Sources 49 minutes Module 4: Skylake Core i7 v6 Desktop 25 minutes Module 5: Haswell E5-2600 v3 Server 13 minutes Module 6: Broadwell Core M SOC Tablet 22 minutes Module 7: Broadwell Xeon E7-8800 v4 Server 13 minutes Module 7b: Cascade Lake-SP 2S Server 57 minutes Module 8: x86 Instruction Set Overview 54 minutes Module 9: x86 Register Set Introduction 52 minutes Module 10: x86 CPU Operating Modes 49 minutes Module 11: Platform Addressing 39 minutes Module 12a: CPU Memory Segmentation Part A 25 minutes Module 12b: CPU Memory Segmentation Part B 56 minutes Module 13a: x86 Paging and TLBs 45 minutes Module 13b: x86 Paging and TLBs 52 minutes Module 13c: x86 Paging and TLBs 53 minutes Module 14: CPU Internal Architecture Overview 44 minutes Module 15: CPU Microarchitecture 38 minutes Module 16: Cache Basics 59 minutes Module 17: Cache Regions & CPU Conduct 58 minutes Module 18: Cache Hardware Architecture 45 minutes Module 19: Cache and Memory QoS 37 minutes Module 20: Other Cache Topics 31 minutes Module 21: CPU and PCH Interface Overview 42 minutes Module 22: Main Memory DRAM 44 minutes Module 23a: QuickPath Interconnect (QPI) 71 minutes Module 23b: QuickPath Interconnect (QPI) 39 minutes Module 24: CPU PCI Express (PCIe) 61 minutes Module 25: PCI Configuration Space 73 minutes Module 26: Interrupts: Intro and Controller History 48 minutes Module 27: Interrupts: Local APIC Basics 38 minutes Module 28: Interrupts: Delivery Options 34 minutes Module 29: Interrupts: MSIs, Interrupt Remapping and IPIs 54 minutes Module 30a: Overview of Virtualization Support 47 minutes Module 30b: Overview of Virtualization Support 32 minutes Module 31: CPU Performance Monitoring 43 minutes Module 32: Machine Check Architecture (MCA) 44 minutes Module 33a: System Management Mode (SMM) Details 57 minutes Module 33b: System Management Mode (SMM) Details 63 minutes Module 34: Microcode Update 13 minutes Module 35: PCH Internal Architecture 40 minutes Module 36: Platform USB Interfaces 34 minutes Module 37: Platform SATA Interfaces 56 minutes Module 38: Platform SMBus Interfaces 42 minutes Module 39: Platform SPI Interface 17 minutes Module 40a: Platform Power Management Part A 34 minutes Module 40b: Platform Power Management Part B 44 minutes Module 41: Platform Thermal Management 28 minutes Module 42a: Intel Optane Memory 56 minutes Module 42b: Intel Optane Memory 42 minutes Module 42c: Intel Optane Memory 55 minutes
Intel® 64 and IA-32 Architectures Software Developer Manuals
Overview
These manuals describe the architecture and programming environment of the Intel® 64 and IA-32 architectures.
Electronic versions of these documents allow you to quickly get to the information you need and print only the pages you want. The Intel® 64 and IA-32 architectures software developer's manuals are now available for download via one combined volume, a four volume set or a ten volume set. All content is identical in each set; see details below.
At present, downloadable PDFs of all volumes are at version 077. The downloadable PDF of the Intel® 64 and IA-32 architectures optimization reference manual is at version 045. Additional related specifications, application notes, and white papers are also available for download.
Note If you would like to be notified of updates to the Intel® 64 and IA-32 architectures software developer's manuals, you may utilize a third-party service, such as Visualping* tobe notified of changes to this page (please reference 1 below).
Note We are no longer offering the Intel® 64 and IA-32 architectures software developer’s manuals on CD-ROM. Hard copy versions of the manual are available for purchase via a print-on-demand fulfillment model through a third-party vendor, Lulu (please reference 1 and 2 below):
Terms of use The order price of each volume is set by the print vendor; Intel uploads the finalized master with zero royalty.
Combined Volume Set of Intel® 64 and IA-32 Architectures Software Developer’s Manuals
Document Description Intel® 64 and IA-32 Architectures Software Developer’s Manual Combined Volumes: 1, 2A, 2B, 2C, 2D, 3A, 3B, 3C, 3D, and 4 This document contains the following:
Volume 1: Describes the architecture and programming environment of processors supporting IA-32 and Intel® 64 architectures.
Volume 2: Includes the full instruction set reference, A-Z. Describes the format of the instruction and provides reference pages for instructions.
Volume 3: Includes the full system programming guide, parts 1, 2, 3, and 4. Describes the operating-system support environment of Intel® 64 and IA-32 architectures, including: memory management, protection, task management, interrupt and exception handling, multi-processor support, thermal and power management features, debugging, performance monitoring, system management mode, virtual machine extensions (VMX) instructions, Intel® Virtualization Technology (Intel® VT), and Intel® Software Guard Extensions (Intel® SGX).
NOTE: Performance monitoring events can be found here:
Volume 4: Describes the model-specific registers of processors supporting IA-32 and Intel® 64 architectures. Intel® 64 and IA-32 Architectures Software Developer's Manual Documentation Changes Describes bug fixes made to the Intel® 64 and IA-32 architectures software developer's manual between versions.
NOTE: This change document applies to all Intel® 64 and IA-32 architectures software developer’s manual sets (combined volume set, 4 volume set, and 10 volume set).
Four-Volume Set of Intel® 64 and IA-32 Architectures Software Developer’s Manuals
This set consists of volume 1, volume 2 (combined 2A, 2B, 2C, and 2D), volume 3 (combined 3A, 3B, 3C, and 3D), and volume 4. This set allows for easier navigation of the instruction set reference and system programming guide through functional cross-volume table of contents, references, and index.
Ten-Volume Set of Intel® 64 and IA-32 Architectures Software Developer's Manuals
This set contains the same information as the four-volume set, but separated into ten smaller PDFs: volume 1, volume 2A, volume 2B, volume 2C, volume 2D, volume 3A, volume 3B, volume 3C, volume 3D, and volume 4. This set is better suited to those with slower connection speeds.
Intel® Architecture Instruction Set Extensions Programming Reference
Document Description Intel® Architecture Instruction Set Extensions Programming Reference This document covers new instructions and features slated for future Intel® processors.
Software Optimization Reference Manual
Public Repository on GitHub
Uncore Performance Monitoring Reference Manuals
Related Specifications, Application Notes, and White Papers
Mercury Research: AMD closes 2021 with record x86 CPU market share at 25.6%
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Advanced Micro Devices made sizable gains in market share against Intel in the x86 processor market, according to year-end data from Mercury Research. In the fourth quarter of 2021, it had a record 25.6% share of the market for processors using the x86 architecture.
AMD has been gaining share (in the combined PC, game console, and internet of things x86 chip market) against Intel for 11 quarters now thanks to the acceptance of its Zen architecture, which enables AMD chips to process more instructions per clock cycle. But in Q4 Intel took back some mobile market share.
Every segment of the x86 (Intel-compatible) processor market grew in the fourth quarter of 2021. Mobile central processing unit (CPU) shipments were up weakly, however the remaining segments all had strong growth. The overall market is down on-year, however, largely due to the collapse in entry-level mobile processor volume that occurred in mid-2021.
For the full PC processor market, which includes Arm devices for Chromebooks and Apple’s M1-based Macs, the overall market grew at a healthy rate. The x86 market grew 16% in 2021, said Dean McCarron, president of Mercury Research, in an email to VentureBeat.
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“While this is nominally a share discussion, I would mention that the total X86 market set a record for both units and revenue, as did the server and mobile CPU markets among others,” McCarron said. “Moving beyond just x86 clients and servers, the total market size, including x86 internet of things and system-on-chip products such as those used for gaming consoles, and ARM-based Chromebooks and Apple’s M1-based Macs, was an even 500 million units in 2021.”
He added, “Without ARM the x86 figure alone is approximately 471 million units. Revenue for just x86 processors was $74 billion for the year, up 10.7 percent from 2020’s $66.6 billion.”
For all-inclusive share, which counts not only PC client CPUs and servers but also IoT and semi-custom products used in items like gaming consoles, AMD gained share in the fourth quarter, largely due to a very large increase in gaming console shipments (AMD’s chips are used in the Sony PlayStation 5 and Microsoft Xbox Series X/S).
As a result of that increase, AMD reached a new record high for overall share — 25.6% — in the fourth quarter of 2021, beating the prior record of 25.3% set fifteen years ago in the fourth quarter of 2006.
Mercury Research’s Q4 numbers in the PC processor market.
All-inclusive share on an annual basis (not in the tables) was 76.7% for Intel and 23.3% for AMD, was a 3.6 point move up for AMD and down for Intel compared to 2020 results of 80.3% for Intel and 19.6% for AMD. Annual share was
also a new record high for AMD, beating the 2006 record of 22.9% percent.
In Q4, Intel partially recovered from the downturn it experienced in mobile CPUs in the third quarter, and the company had very strong growth in desktop shipments. This resulted in Intel’s growth in desktop and mobile CPUs outpacing AMD’s, with Intel gaining share in mobile CPUs, desktop CPUs, and overall client.
AMD continued to expand its server shipments more quickly than Intel — both suppliers experienced good growth in the fourth quarter — resulting in the 11th consecutive quarter of server CPU share gain for AMD.
Intel’s 12th Gen Core mobile processors are 40% faster than the previous generation.
Mercury’s estimate for ARM PC client share (including Chromebooks and Apple’s M1 based Macs with X86 desktop and mobile CPUs in the total client size estimate) is 9.5%, up from 8.3% last quarter and nearly triple the 3.4% from a year ago. Apple had very strong growth in the quarter, so the gains were driven by higher M1 unit volumes rather than Chromebook ARM processors.
As an aside, VIA/Zhaoxin share rounds to zero in all segments. It’s highly probable Zhaoxin’s share is growing, but Mercury has extremely limited visibility into this small segment of the CPU business.
Asked about Apple’s impact in switching to Arm-based chips with the M1, McCarron said, “Had Apple not moved to M1, yes, the X86 market would be larger — I wouldn’t exactly spin that as the x86 market having lower growth, though. Growth in 2021 wasn’t meaningfully lower than what we saw in 2020, as both were in the mid-teens, far higher than average — the five year average for annual x86 growth prior to 2020 was -4.1% per year.
AMD’s most recent low for annual share was 12.7% in 2015. The most recent low since the prior record high quarter in 2006 was 11.6% in the first quarter of 2016, and their record low was 5.5% in the second quarter of 1997.
Most of the decline that happened for Intel in Q3 was due to mobile Celeron. The increase in Q4 shipments was due to non-Celeron mobile products, primarily the Tiger Lake core mobile parts, or the i5/i7 1100 series. In desktop, it was a mix of Comet Lake and Rocket Lake parts that ramped higher.